Silicon-On-Insulator (SOI) CMOS technology is recognized worldwide as “silicon integrated circuit technology of 21th century.” Due to its unique structure, excellent dielectric isolation between devices, and isolation of silicon under field region by buried oxide layer, the SOI CMOS technology has many advantages compared with conventional bulk-silicon CMOS technology.
The structure and process of the SOI CMOS technology are relatively simple. For bulk-silicon CMOS devices, isolation between devices and isolation between a device and a substrate are implemented by reversely biased PN junctions, which may generate leakage current. Also, the bulk-silicon CMOS device cannot be highly integrated. In contrast, SOI CMOS devices are isolated fully by dielectric structures, and thus field regions and well structures as in the bulk-silicon CMOS circuit are not necessary. As a result, the structure is compact and the process is simpler.
The SOI CMOS technology avoids latch-up effect. The bulk-silicon CMOS technology is based on n-well or p-well. Parasitic “pnpn” structure between the well and the substrate will be activated under certain conditions and cause the latch-up effect. The full dielectric isolation of the SOI terminal avoids the well structure and thus avoids the latch-up effect.
The SOI CMOS technology has good performance at high temperature. The PN junction of the SOI CMOS device is a side junction, which has an effective junction area and a spatial charge region much smaller than that of the bulk-silicon device. As a result, it has better performance at high temperature than the bulk-silicon device under a same heat-induced leakage condition. The SOI device or circuit has three advantages over the bulk-silicon device under a high-temperature operation condition: no heat-activated latch-up effect, small leakage current, and small variation of threshold voltage vs temperature for a thin-film full depletion device.
The SOI CMOS technology has a high speed, a low operation voltage, and a low power consumption. The source-drain junction depth of the SOI device is limited only by the thickness of the top silicon film and thus it is easy to form a shallow junction having a small source/drain area. The parasitic capacitance is small due to the full dielectric isolation.
In summary, the SOI CMOS integrated circuit has small parasitic parameters and substantially no latch-up effect and thus has become a main technology in researching and developing ultra-high scale integrated circuit of high speed, low power consumption, high integration, and high reliability. It is also one of the main technologies for the next generation of system integration with low power consumption and high reliability. Therefore, it has attracted worldwide attention.
In the modern society, more and more people are experiencing inconvenience caused by hearing disorder. According to an authoritative report, about thirty million people all around the world are experiencing the hearing disorder and the population is increasing quickly. Thus, there is a need for a low-cost and high-performance medical device, such as a hearing aid, to alleviate or address various problems caused by the hearing disorder.
Analog front circuit is attracting more and more attention with respect to its structure and design method as the most important module in the input end of the medical hearing aid device. Currently, the medical hearing aid device typically comprises an automatic gain control loop in its analog front circuit. The automatic gain control loop implements feedback using fully customized analog circuits. The analog feedback circuit usually comprises circuit modules such as a peek filter, an analog integrator, an analog comparator, and an analog filter. Such an implementation has advantages in that modules are relatively independent from each other and less interrelated, which may facilitate variation of the circuit. However, the feedback loop is difficult to implement due to limitations of the analog circuit. Meanwhile, it also has disadvantages such as high noise, low control accuracy, and high power consumption. Sigma_delta analog-to-digital converter using single-bit quantization can be used to achieve high accuracy. However, it is usually implemented by high-order integrator and the power consumption is high.
In view of the foregoing, the present disclosure provides an SOI analog front circuit with a novel structure, high performance, and low power consumption for the medical hearing aid device to satisfy the requirement of a digital hearing aid device with high accuracy, low power consumption, and high reliability.